//==========================================================================
// Copyright (c) 2000-2008,  Elastos, Inc.  All Rights Reserved.
//==========================================================================
#ifndef __MEMDEFS_H__
#define __MEMDEFS_H__

/*  Copyright 2002 Intel Corp. */
/*++
** INTEL CONFIDENTIAL
** Copyright 2000-2003 Intel Corporation All Rights Reserved.
**
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** or its suppliers or licensors.  Title to the Material remains with
** Intel Corporation or its suppliers and licensors. The Material contains
** trade secrets and proprietary and confidential information of Intel
** or its suppliers and licensors. The Material is protected by worldwide
** copyright and trade secret laws and treaty provisions. No part of the
** Material may be used, copied, reproduced, modified, published, uploaded,
** posted, transmitted, distributed, or disclosed in any way without Intel
** prior express written permission.
**
** No license under any patent, copyright, trade secret or other intellectual
** property right is granted to or conferred upon you by disclosure or
** delivery of the Materials, either expressly, by implication, inducement,
** estoppel or otherwise. Any license under such intellectual property rights
** must be express and approved by Intel in writing.


Module Name:  MEMDefs.h

Abstract:
  Contains address definitions for the separate reserved
  memory areas, including the DMA buffer areas

Notes:

--*/

//
// Base Address for Reserved Memory Areas
// Note:  These addresses below must be in sync with config.bib and bvd1.inc

#define MMXIP_MEMMAP
#define FRAME_BUFFER_IN_SRAM

#ifdef MMXIP_MEMMAP
//#define MEM_BASE_PHYSICAL           0xA3A00000
#define MEM_BASE_PHYSICAL           0xA1000000
#define MEM_BASE_C_VIRTUAL          0x9A600000  // 96C0 0000 + 03A0 0000
#define EDBG_PHYSICAL_MEMORY_START  0x9ABE0000      // Ethernet Debugger Pool Address
#else
//#define MEM_BASE_PHYSICAL           0xA3CB8000
#define MEM_BASE_PHYSICAL           0xA0110000
#define MEM_BASE_C_VIRTUAL          0x80000000
#define EDBG_PHYSICAL_MEMORY_START  0x83F8D000      // Ethernet Debugger Pool Address
#endif //MMXIP_MEMMAP

#define MEM_BASE_U_VIRTUAL          (MEM_BASE_C_VIRTUAL+CACHED_TO_UNCACHED_OFFSET)


#define SLEEP_SAVE_BYTES            (0x1000)
#define SLEEP_TYPE_OFFSET           (SLEEP_SAVE_BYTES-4)

#ifdef MMXIP_MEMMAP
#define AUDIO_DMA_OFFSET            (0x2B0000)
#define SLEEP_SAVE_OFFSET           (0x2BA000)
#define DRIVER_GLOBALS_OFFSET       (0x2BB000)
#define	GDE_BUFFER_OFFSET			(0x4D6000)  // UNUSED_BUF
#else
#define AUDIO_DMA_OFFSET            (0x0)
#define SLEEP_SAVE_OFFSET           (0xA000)
#define DRIVER_GLOBALS_OFFSET       (0xB000)
#define	GDE_BUFFER_OFFSET			(0x1C1000)	// UNUSED_BUF
#endif //MMXIP_MEMMAP

#ifdef FRAME_BUFFER_IN_SRAM
#define LCD_MEM_BASE_PHYSICAL       IM_STORAGE_BASE_PHYSICAL
#define LCD_MEM_BASE_U_VIRTUAL      IM_STORAGE_BASE_U_VIRTUAL
#define DISPLAY_DMA_OFFSET          (0x0)
#else
#define LCD_MEM_BASE_PHYSICAL       MEM_BASE_PHYSICAL
#define LCD_MEM_BASE_U_VIRTUAL      MEM_BASE_U_VIRTUAL
#ifdef MMXIP_MEMMAP
#define DISPLAY_DMA_OFFSET          (0x0)
#else
#define DISPLAY_DMA_OFFSET          (0x48000)
#endif //MMXIP_MEMMAP
#endif

//
// Internal Memory (IM) Save Area definitions
//
// 4 x 64k for the 4 IM segments during low-power modes
#ifdef MMXIP_MEMMAP
#define IM_SAVE_OFFSET               (0x2BD000)
#else
#define IM_SAVE_OFFSET               (0x178000)
#endif //MMXIP_MEMMAP

#define IM_SAVE_PHYSICAL        (MEM_BASE_PHYSICAL+IM_SAVE_OFFSET)
#define IM_SAVE_C_VIRTUAL       (MEM_BASE_C_VIRTUAL+IM_SAVE_OFFSET)
#define IM_SAVE_U_VIRTUAL       (MEM_BASE_U_VIRTUAL+IM_SAVE_OFFSET)
#define IM_BANK_SIZE            (0x10000)   // Same as XLLP_IM_BANK_SIZE


#ifdef USBOHCI_DMA_IN_SRAM
//
// If in SRAM, the USB OHCI DMA buffer gets the last 64K of the 256k SRAM
//
#define USBOHCI_DMA_OFFSET			(0x30000)
#define USBOHCI_DMA_BASE_PHYSICAL	(IM_STORAGE_BASE_PHYSICAL+USBOHCI_DMA_OFFSET)
#define USBOHCI_DMA_BASE_U_VIRTUAL	(IM_STORAGE_BASE_U_VIRTUAL+USBOHCI_DMA_OFFSET)
#else
//
// If not in SRAM, the USB OHCI DMA buffer is in the SDRAM region specified in config.bib
//
#ifdef MMXIP_MEMMAP
#define USBOHCI_DMA_OFFSET			(0x2FD000)
#else
#define USBOHCI_DMA_OFFSET			(0x1B8000)
#endif //MMXIP_MEMMAP
#define USBOHCI_DMA_BASE_PHYSICAL	(MEM_BASE_PHYSICAL+USBOHCI_DMA_OFFSET)
#define USBOHCI_DMA_BASE_U_VIRTUAL	(MEM_BASE_U_VIRTUAL+USBOHCI_DMA_OFFSET)
#endif //USBOHCI_DMA_IN_SRAM

//
// Camera DMA Definitions
//
#ifdef MMXIP_MEMMAP
#define CAMERA_DMA_OFFSET						(0x306000)
#else
#define CAMERA_DMA_OFFSET						(0x1C1000)
#endif																									// MMXIP_MEMMAP

// camera buffer set for 320x240x16bpp x 3 buffers
#define CAMERA_DMA_BUFFER_SIZE					(0x70800)
#define CAM_DMA_BUFFER_PHYSICAL					(MEM_BASE_PHYSICAL	+ CAMERA_DMA_OFFSET)
#define CAM_DMA_BUFFER_U_VIRTUAL				(MEM_BASE_U_VIRTUAL + CAMERA_DMA_OFFSET)
#define CAM_DMA_DESCRIPTOR_BASE_PHYSICAL		(CAM_DMA_BUFFER_PHYSICAL 	+ CAMERA_DMA_BUFFER_SIZE)
#define CAM_DMA_DESCRIPTOR_BASE_U_VIRTUAL		(CAM_DMA_BUFFER_U_VIRTUAL  	+ CAMERA_DMA_BUFFER_SIZE)


//
// Sleep Save Area definitions
//
#define SLEEP_SAVE_PHYSICAL     (MEM_BASE_PHYSICAL+SLEEP_SAVE_OFFSET)
#define SLEEP_SAVE_C_VIRTUAL    (MEM_BASE_C_VIRTUAL+SLEEP_SAVE_OFFSET)
#define SLEEP_SAVE_U_VIRTUAL    (MEM_BASE_U_VIRTUAL+SLEEP_SAVE_OFFSET)

//
// Driver Globals Area
//
#define DRIVER_GLOBALS_PHYSICAL     (MEM_BASE_PHYSICAL+DRIVER_GLOBALS_OFFSET)
#define DRIVER_GLOBALS_C_VIRTUAL    (MEM_BASE_C_VIRTUAL+DRIVER_GLOBALS_OFFSET)
#define DRIVER_GLOBALS_U_VIRTUAL    (DRIVER_GLOBALS_C_VIRTUAL+CACHED_TO_UNCACHED_OFFSET)

//
// DMA Descriptor offset
//
#define DMA_DESC_SIZE               (0x20)

//
// LCD DMA Definitions for frame buffer located in SDRAM
//
// Must be aligned on 128-bit boundary. (Bits 0-3 must be 0)
// Allocate a minimum of 0x14 bytes each.
//
#define DMA_CHANNEL_0_FRAME_DESCRIPTOR_BASE_PHYSICAL        (LCD_MEM_BASE_PHYSICAL+DISPLAY_DMA_OFFSET)  // 00-1F
#define DMA_CHANNEL_0_FRAME_DESCRIPTOR_BASE_VIRTUAL         (LCD_MEM_BASE_U_VIRTUAL+DISPLAY_DMA_OFFSET)

#define DMA_CHANNEL_1_FRAME_DESCRIPTOR_BASE_PHYSICAL        (DMA_CHANNEL_0_FRAME_DESCRIPTOR_BASE_PHYSICAL+DMA_DESC_SIZE)    // 20-3F
#define DMA_CHANNEL_1_FRAME_DESCRIPTOR_BASE_VIRTUAL         (DMA_CHANNEL_0_FRAME_DESCRIPTOR_BASE_VIRTUAL+DMA_DESC_SIZE)

#define DMA_CHANNEL_0_ALT_FRAME_DESCRIPTOR_BASE_PHYSICAL    (DMA_CHANNEL_1_FRAME_DESCRIPTOR_BASE_PHYSICAL+DMA_DESC_SIZE)    // 40-5F
#define DMA_CHANNEL_0_ALT_FRAME_DESCRIPTOR_BASE_VIRTUAL     (DMA_CHANNEL_1_FRAME_DESCRIPTOR_BASE_VIRTUAL+DMA_DESC_SIZE)

#define PALETTE_FRAME_DESCRIPTOR_BASE_PHYSICAL              (DMA_CHANNEL_0_ALT_FRAME_DESCRIPTOR_BASE_PHYSICAL+DMA_DESC_SIZE)    // 60-7F
#define PALETTE_FRAME_DESCRIPTOR_BASE_VIRTUAL               (DMA_CHANNEL_0_ALT_FRAME_DESCRIPTOR_BASE_VIRTUAL+DMA_DESC_SIZE)

#define SDRAM_DMA_CHANNEL_2_Y_FRAME_DESCRIPTOR_BASE_PHYSICAL	(PALETTE_FRAME_DESCRIPTOR_BASE_PHYSICAL+DMA_DESC_SIZE)    // 80 - 9F
#define SDRAM_DMA_CHANNEL_2_Y_FRAME_DESCRIPTOR_BASE_VIRTUAL		(PALETTE_FRAME_DESCRIPTOR_BASE_VIRTUAL+DMA_DESC_SIZE)

#define SDRAM_DMA_CHANNEL_3_Cb_FRAME_DESCRIPTOR_BASE_PHYSICAL	(SDRAM_DMA_CHANNEL_2_Y_FRAME_DESCRIPTOR_BASE_PHYSICAL+DMA_DESC_SIZE) // A0 - BF
#define SDRAM_DMA_CHANNEL_3_Cb_FRAME_DESCRIPTOR_BASE_VIRTUAL	(SDRAM_DMA_CHANNEL_2_Y_FRAME_DESCRIPTOR_BASE_VIRTUAL+DMA_DESC_SIZE)

#define SDRAM_DMA_CHANNEL_4_Cr_FRAME_DESCRIPTOR_BASE_PHYSICAL	(SDRAM_DMA_CHANNEL_3_Cb_FRAME_DESCRIPTOR_BASE_PHYSICAL+DMA_DESC_SIZE) // C0 - DF
#define SDRAM_DMA_CHANNEL_4_Cr_FRAME_DESCRIPTOR_BASE_VIRTUAL	(SDRAM_DMA_CHANNEL_3_Cb_FRAME_DESCRIPTOR_BASE_VIRTUAL+DMA_DESC_SIZE)


#define SRAM_DMA_CHANNEL_2_Y_FRAME_DESCRIPTOR_BASE_PHYSICAL	 (IM_STORAGE_BASE_PHYSICAL)    // 80 - 9F
#define SRAM_DMA_CHANNEL_2_Y_FRAME_DESCRIPTOR_BASE_VIRTUAL	 (IM_STORAGE_BASE_U_VIRTUAL)

#define SRAM_DMA_CHANNEL_3_Cb_FRAME_DESCRIPTOR_BASE_PHYSICAL (SRAM_DMA_CHANNEL_2_Y_FRAME_DESCRIPTOR_BASE_PHYSICAL+DMA_DESC_SIZE) // A0 - BF
#define SRAM_DMA_CHANNEL_3_Cb_FRAME_DESCRIPTOR_BASE_VIRTUAL	 (SRAM_DMA_CHANNEL_2_Y_FRAME_DESCRIPTOR_BASE_VIRTUAL+DMA_DESC_SIZE)

#define SRAM_DMA_CHANNEL_4_Cr_FRAME_DESCRIPTOR_BASE_PHYSICAL (SRAM_DMA_CHANNEL_3_Cb_FRAME_DESCRIPTOR_BASE_PHYSICAL+DMA_DESC_SIZE) // C0 - DF
#define SRAM_DMA_CHANNEL_4_Cr_FRAME_DESCRIPTOR_BASE_VIRTUAL	 (SRAM_DMA_CHANNEL_3_Cb_FRAME_DESCRIPTOR_BASE_VIRTUAL+DMA_DESC_SIZE)




//
// Must be aligned on 64-bit boundary. (Bits 0-2 must be 0)
// Allocate 0x400 bytes. (256 x 4 bytes/pixel)
//
#define DMA_PALETTE_SIZE            (0x400)
#define PALETTE_BUFFER_BASE_PHYSICAL                        (SDRAM_DMA_CHANNEL_4_Cr_FRAME_DESCRIPTOR_BASE_PHYSICAL+DMA_DESC_SIZE)  // E0-2DF
#define PALETTE_BUFFER_BASE_VIRTUAL                         (SDRAM_DMA_CHANNEL_4_Cr_FRAME_DESCRIPTOR_BASE_VIRTUAL+DMA_DESC_SIZE)

// Must be aligned on 64-bit boundary. (Bits 0-2 must be 0)
// Allocate 0x96000 bytes. (640 x 480 x (2 bytes/pixel))
//#define DMA_FRAME_SIZE                  (0x96000)
// Allocate 0x25800 bytes. (240 x 320 x (2 bytes/pixel))
#define DMA_FRAME_SIZE					               (0x25800)
#define FRAME_BUFFER_0_BASE_PHYSICAL                        (PALETTE_BUFFER_BASE_PHYSICAL+DMA_PALETTE_SIZE)     // 2E0-962DF
#define FRAME_BUFFER_0_BASE_VIRTUAL                         (PALETTE_BUFFER_BASE_VIRTUAL+DMA_PALETTE_SIZE)

// Must be aligned on 64-bit boundary. (Bits 0-2 must be 0)
// Allocate 0x96000 bytes. (640 x 480 x (2 bytes/pixel))
#define FRAME_BUFFER_1_BASE_PHYSICAL                        (FRAME_BUFFER_0_BASE_PHYSICAL+DMA_FRAME_SIZE)       // 962E0-12C2DF
#define FRAME_BUFFER_1_BASE_VIRTUAL                         (FRAME_BUFFER_0_BASE_VIRTUAL+DMA_FRAME_SIZE)

#define OVERLAY2_SDRAM_PHYSICAL_BASE_ADDRESS	(FRAME_BUFFER_1_BASE_PHYSICAL+DMA_FRAME_SIZE)
#define OVERLAY2_SDRAM_VIRTUAL_BASE_ADDRESS		(FRAME_BUFFER_1_BASE_VIRTUAL+DMA_FRAME_SIZE)

#define OVERLAY2_SRAM_PHYSICAL_BASE_ADDRESS		(SRAM_DMA_CHANNEL_4_Cr_FRAME_DESCRIPTOR_BASE_PHYSICAL+DMA_DESC_SIZE)
#define OVERLAY2_SRAM_VIRTUAL_BASE_ADDRESS		(SRAM_DMA_CHANNEL_4_Cr_FRAME_DESCRIPTOR_BASE_VIRTUAL+DMA_DESC_SIZE)

//
// Audio DMA Definitions
//
#define AUDIO_BUFFER_SIZE  0x1000

#define DMA_BUFFER_PHYSICAL                     (MEM_BASE_PHYSICAL+AUDIO_DMA_OFFSET)
#define DMA_BUFFER_VIRTUAL                      (MEM_BASE_U_VIRTUAL+AUDIO_DMA_OFFSET)

#define DMA_XMIT_A_BUFFER_BASE_PHYSICAL         (DMA_BUFFER_PHYSICAL)
#define DMA_XMIT_A_BUFFER_BASE_VIRTUAL          (DMA_BUFFER_VIRTUAL)

#define DMA_XMIT_B_BUFFER_BASE_PHYSICAL         (DMA_XMIT_A_BUFFER_BASE_PHYSICAL+AUDIO_BUFFER_SIZE)
#define DMA_XMIT_B_BUFFER_BASE_VIRTUAL          (DMA_XMIT_A_BUFFER_BASE_VIRTUAL +AUDIO_BUFFER_SIZE)

#define DMA_RCV_A_BUFFER_BASE_PHYSICAL          (DMA_XMIT_B_BUFFER_BASE_PHYSICAL+AUDIO_BUFFER_SIZE)
#define DMA_RCV_A_BUFFER_BASE_VIRTUAL           (DMA_XMIT_B_BUFFER_BASE_VIRTUAL +AUDIO_BUFFER_SIZE)

#define DMA_RCV_B_BUFFER_BASE_PHYSICAL          (DMA_RCV_A_BUFFER_BASE_PHYSICAL+AUDIO_BUFFER_SIZE)
#define DMA_RCV_B_BUFFER_BASE_VIRTUAL           (DMA_RCV_A_BUFFER_BASE_VIRTUAL +AUDIO_BUFFER_SIZE)


#define DMA_MIC_A_BUFFER_BASE_PHYSICAL          (DMA_RCV_B_BUFFER_BASE_PHYSICAL+AUDIO_BUFFER_SIZE)
#define DMA_MIC_A_BUFFER_BASE_VIRTUAL           (DMA_RCV_B_BUFFER_BASE_VIRTUAL +AUDIO_BUFFER_SIZE)

#define DMA_MIC_B_BUFFER_BASE_PHYSICAL          (DMA_MIC_A_BUFFER_BASE_PHYSICAL+AUDIO_BUFFER_SIZE)
#define DMA_MIC_B_BUFFER_BASE_VIRTUAL           (DMA_MIC_A_BUFFER_BASE_VIRTUAL +AUDIO_BUFFER_SIZE)

#define DMA_XMIT_A_DESCRIPTOR_BASE_PHYSICAL     (DMA_MIC_B_BUFFER_BASE_PHYSICAL+AUDIO_BUFFER_SIZE) //temp check, leave room
#define DMA_XMIT_A_DESCRIPTOR_BASE_VIRTUAL      (DMA_MIC_B_BUFFER_BASE_VIRTUAL +AUDIO_BUFFER_SIZE)

#define DMA_XMIT_B_DESCRIPTOR_BASE_PHYSICAL     (DMA_XMIT_A_DESCRIPTOR_BASE_PHYSICAL+DMA_DESC_SIZE)
#define DMA_XMIT_B_DESCRIPTOR_BASE_VIRTUAL      (DMA_XMIT_A_DESCRIPTOR_BASE_VIRTUAL +DMA_DESC_SIZE)

#define DMA_RCV_A_DESCRIPTOR_BASE_PHYSICAL      (DMA_XMIT_B_DESCRIPTOR_BASE_PHYSICAL+DMA_DESC_SIZE)
#define DMA_RCV_A_DESCRIPTOR_BASE_VIRTUAL       (DMA_XMIT_B_DESCRIPTOR_BASE_VIRTUAL +DMA_DESC_SIZE)

#define DMA_RCV_B_DESCRIPTOR_BASE_PHYSICAL      (DMA_RCV_A_DESCRIPTOR_BASE_PHYSICAL+DMA_DESC_SIZE)
#define DMA_RCV_B_DESCRIPTOR_BASE_VIRTUAL       (DMA_RCV_A_DESCRIPTOR_BASE_VIRTUAL +DMA_DESC_SIZE)

#define DMA_MIC_A_DESCRIPTOR_BASE_PHYSICAL      (DMA_RCV_B_DESCRIPTOR_BASE_PHYSICAL+DMA_DESC_SIZE)
#define DMA_MIC_A_DESCRIPTOR_BASE_VIRTUAL       (DMA_RCV_B_DESCRIPTOR_BASE_VIRTUAL +DMA_DESC_SIZE)

#define DMA_MIC_B_DESCRIPTOR_BASE_PHYSICAL      (DMA_MIC_A_DESCRIPTOR_BASE_PHYSICAL+DMA_DESC_SIZE)
#define DMA_MIC_B_DESCRIPTOR_BASE_VIRTUAL       (DMA_MIC_A_DESCRIPTOR_BASE_VIRTUAL +DMA_DESC_SIZE)

//
//
//  GDE Buffer Definitions
//
#define GDE_BUFFER_PHYSICAL                     (MEM_BASE_PHYSICAL +GDE_BUFFER_OFFSET)
#define GDE_BUFFER_VIRTUAL                      (MEM_BASE_U_VIRTUAL+GDE_BUFFER_OFFSET)

#endif


